U1
Intake stage
Capture the signal before it decays
Hardware knowledge arrives as noise: a Slack thread, a scope photo, a whiteboard from a standup that three people remember differently. Intake buffers all of it into one net and holds it at a known level until someone is ready to route it.
- NET_IN0
- NET_CLK
- NET_D3
- NET_VDD
Buffered
12 sources
Threads, tickets, bench logs and CAD comments land on the same rail.
Latched
0 loss
Nothing is discarded before a human assigns it a destination pin.
U2
Routing fabric
Length-matched paths, not folders
A folder tree assumes every document has one home. A board assumes every signal has many destinations and one impedance budget. Vireo routes each note as a net with declared endpoints — the spec pin, the test pin, the manufacturing pin — so a change propagates instead of getting filed.
Differential
±2 mil
Paired revisions travel together; a spec never lands without its test.
Plane
Layer 2
Shared context sits under everything as an uninterrupted reference.
Stitching
64 vias
Cross-team handoffs punch through layers instead of routing around.
U3
Netlist
Continuity report, rev D
Hover any row or any pad above — the whole net lights up across the board, including the copper between modules. This is the same connectivity model the routing fabric uses; there is no separate index to keep in sync.
U4
Test point
Put a probe on your own stack
Send us a net name and we will route a sandbox board against your repo within a working day. No connector required — we bring the harness.